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RPM: verilator
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Current version: 5.012-alt1.1
Build date: 22 july 2023, 06:50 ( 38.8 weeks ago )
Size: 1952.50 Kb
Home page: https://www.veripool.org/wiki/verilator
License: LGPLv3 or Artistic-2.0
Summary: A fast and free Verilog HDL simulator
Description:
List of contributors List of rpms provided by this srpm:
ACL:
Build date: 22 july 2023, 06:50 ( 38.8 weeks ago )
Size: 1952.50 Kb
Home page: https://www.veripool.org/wiki/verilator
License: LGPLv3 or Artistic-2.0
Summary: A fast and free Verilog HDL simulator
Description:
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and
Synthesis assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is especially well
suited to generate executable models of CPUs for embedded software design teams.
Current maintainer: Ilya Kurdyukov simulators. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and
Synthesis assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is especially well
suited to generate executable models of CPUs for embedded software design teams.
List of contributors List of rpms provided by this srpm:
- verilator
- verilator-debuginfo
- verilator-doc