Group :: Engineering
RPM: iverilog
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A versão atual: 12.0-alt1
Data da compilação: 10 janeiro 2023, 16:14 ( 66.5 weeks ago )
Tamanho:: 1942.54 Kb
Home page: http://iverilog.icarus.com
Licença: GPLv2
Sumário: Verilog simulation and synthesis tool
Descrição:
Lista dos contribuidores Lista dos rpms provida por esta srpm:
ACL:
Data da compilação: 10 janeiro 2023, 16:14 ( 66.5 weeks ago )
Tamanho:: 1942.54 Kb
Home page: http://iverilog.icarus.com
Licença: GPLv2
Sumário: Verilog simulation and synthesis tool
Descrição:
Icarus Verilog is a Verilog simulation and synthesis tool. It operates
as a compiler, compiling source code written in Verilog (IEEE-1364)
into some target format. For batch simulation, the compiler can generate
an intermediate form called vvp assembly. This intermediate form is
executed by the ``vvp'' command. For synthesis, the compiler generates
netlists in the desired format. It supports the 1995, 2001 and 2005
versions of the standard, portions of SystemVerilog, and some extensions.
Mantenedor currente: Egor Ignatov as a compiler, compiling source code written in Verilog (IEEE-1364)
into some target format. For batch simulation, the compiler can generate
an intermediate form called vvp assembly. This intermediate form is
executed by the ``vvp'' command. For synthesis, the compiler generates
netlists in the desired format. It supports the 1995, 2001 and 2005
versions of the standard, portions of SystemVerilog, and some extensions.
Lista dos contribuidores Lista dos rpms provida por esta srpm:
- iverilog
- iverilog-debuginfo