Group :: Engineering
RPM: verilator
Principal Changelog Spec Patches Sources Download Gear Bugs e FR Repocop
A versão atual: 5.012-alt1.1
Data da compilação: 22 julho 2023, 06:50 ( 35.8 weeks ago )
Tamanho:: 1952.50 Kb
Home page: https://www.veripool.org/wiki/verilator
Licença: LGPLv3 or Artistic-2.0
Sumário: A fast and free Verilog HDL simulator
Descrição:
Lista dos contribuidores Lista dos rpms provida por esta srpm:
ACL:
Data da compilação: 22 julho 2023, 06:50 ( 35.8 weeks ago )
Tamanho:: 1952.50 Kb
Home page: https://www.veripool.org/wiki/verilator
Licença: LGPLv3 or Artistic-2.0
Sumário: A fast and free Verilog HDL simulator
Descrição:
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and
Synthesis assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is especially well
suited to generate executable models of CPUs for embedded software design teams.
Mantenedor currente: Ilya Kurdyukov simulators. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and
Synthesis assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is especially well
suited to generate executable models of CPUs for embedded software design teams.
Lista dos contribuidores Lista dos rpms provida por esta srpm:
- verilator
- verilator-debuginfo
- verilator-doc